Capacitors are elements that are used extensively in semiconductor devices for storing an electrical charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends on a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value of the insulator between the plates, as examples. Capacitors are used in filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor devices.
One type of capacitor is a MIM capacitor, which is frequently used in mixed signal devices and logic semiconductor devices, as examples. MIM capacitors are used to store a charge in a variety of semiconductor devices. MIM capacitors are often used as storage nodes in a memory device, for example. A MIM capacitor is typically formed horizontally on a semiconductor wafer, with two metal plates sandwiching a dielectric layer parallel to the wafer surface.
A prior art MIM capacitor 114 formed in a semiconductor device is shown in FIG. 1. The semiconductor device includes a workpiece 100, which may comprise a semiconductor wafer or substrate having active areas, components or other material layers formed thereon. A plurality of metallization layers are typically formed over the workpiece 100. For example, a top metallization layer Mn may comprise a plurality of conductive lines 122, and an underlying metallization layer M(n-1) may be disposed beneath the top metallization layer Mn. The metallization layer M(n-1) may also comprise a plurality of conductive lines 106 formed therein. An inter-level dielectric (ILD) layer is disposed between the conductive lines 106 and 122, not shown. There may be other metallization layers beneath the metallization layer M(n-1), also not shown, e.g., there may be two to four additional metallization layers disposed beneath metallization layer M(n-1). The metallization layers Mn, M(n-1), and other metallization layers not shown provide an interconnect system, along with vias 104 formed in insulating layer 102 and vias 118 formed in insulating layer 120, for example. The conductive lines 106 and 122 and vias 104 and 118 provide an interconnect means between various components and active regions formed in the workpiece 100 and also provide connection to contacts that will be used to make electrical contact outside the semiconductor device (not shown).
The metallization layers Mn and M(n-1) typically comprise copper or aluminum. Copper has a lower resistance and a higher conductivity than aluminum, but requires damascene processes and more expensive manufacturing processes. Aluminum is typically patterned using a subtractive etch process, for example.
FIG. 1 illustrates a prior art MIM capacitor 114 formed in the via dielectric layer 120. To form the MIM capacitor 114, after conductive lines 106 are formed in metallization layer M(n-1), a conductive material 108 is deposited over the conductive lines 106 and ILD layer disposed between the conductive lines 106 (not shown). The conductive material 108 typically comprises TiN, for example. The conductive material 108 is patterned with a pattern for a MIM capacitor bottom plate using lithography; e.g., a photoresist may be deposited, the photoresist is patterned, and the photoresist is used as a mask while the conductive material 108 is etched to remove portions of the conductive material 108 and form a bottom plate 108. A capacitor dielectric layer 110 is then deposited over the bottom plate 108, and a conductive material 112 is deposited over the capacitor dielectric material 110. The conductive material 112 and dielectric material 110 are patterned with a pattern for the MIM capacitor 114 top plate, as shown, using traditional lithography techniques, for example. An insulating material 120 is deposited over the MIM capacitor 114, and the insulating material 120 is patterned with vias 116 and filled with conductive material, wherein the vias 116 provide electrical contact between the top plate 112 of the MIM capacitor 114 and an overlying conductive line 122 in metallization layer M1.
The prior art method of forming a MIM capacitor 114 shown in FIG. 1 is disadvantageous in that two mask levels are required to pattern the MIM capacitor 114: one mask for the bottom plate 108, and another mask for the top plate 112 and dielectric material 110 patterning. Each metallization layer Mn and M(n-1) and via layers 102 and 116/118 also require a separate mask to pattern conductive lines 122 and 106, and vias 102 and 116/118, respectively.
What is needed in the art is a method of patterning a MIM capacitor and a structure thereof wherein fewer mask levels are required during the fabrication process for forming a MIM capacitor.
Another problem with the prior art MIM capacitor 114 of FIG. 1 is that TiN is used as a bottom electrode 108 material. TiN has a relatively high sheet resistance, which results in an increased resistance for the MIM capacitor 114. Using TiN for a plate of a MIM capacitor limits the use of MIM capacitor devices in high speed and high performance applications, such as radio frequency (RF) applications.
What is also needed is a MIM capacitor with plates having reduced sheet resistance.